The description below relates to DRAMs, although the invention can be applied equally well to SRAMs, and should be construed as such.
DRAMs are typically formed of orthogonally disposed word lines and bit lines, with charge storage cells adjacent each intersection addressed via the wordlines and connected to the bit lines. Each charge storage cell stores a charge received from a bit line when it is addressed, that designates the value (0 or 1) of a bit. Bit lines are typically in a well known folded form, formed of two conductors, that interface a data bus via a sense amplifier and column access devices, such as field effect switches that are addressed via a column decoder.
Pertinent circuitry of a typical prior art DRAM is illustrated in FIG. 1. A charge storage cell is formed of a capacitor 1 connected in series with a field effect transistor 2 (FET) between a voltage supply Vcp and a conductor of a folded bitline 3. The gate of the FET is connected to a wordline 4. The bitline is connected to a sense amplifier 5. Each output conductor of the sense amplifier is connected through an FET 6 to a corresponding conductor of a data bus 8. The gates of FETs 6 are connected together to the output of a column decoder, which provides the control signal Yi, which is a decoded column address signal to those gates.
The conductors of data bus 8 are connected differentially to the input of a read amplifier 9, and to the output of a write amplifier 10. A source of precharge voltage Vcc/2 is connected through FETs 11 to corresponding conductors of the data bus 8. The conductors of data bus 8 are connected together through FET 12. The gates of transistors 11 and 12 are connected together and to a source of a precharge enable control signal, PRE. A write enable signal WMA is provided to a control input of the write amplifier, and a read enable signal RMA is provided to a control input of the read amplifier.
In operation, with reference to the signal waveforms illustrated in FIG. 2A, a precharge enable signal PRE is applied to FETs 11 and 12, causing the data bus to be precharged to Vcc/2. As shown by the waveform PRE, the precharge enable pulse goes to low logic level, and during that interval the decoded column address signal Yi is applied to FETs 6. As a result charge stored on the bitlines resulting from sensing by the sense amplifier of charge stored in a storage cell 1 passes through FETs 6 and is applied differentially to the conductors of data bus 8. The resulting voltage on the data bus conductors is shown in waveform diagram DB/DB,, which is in sawtooth form resulting from the capacitance of the data bus charging in a less than ideal manner, i.e. taking significant time to charge.
After a predetermined time, reading by the read amplifier 9 is enabled, with the application of a read pulse, as shown in waveform Enable RMA, which lasts over an interval terminating prior to the onset of the next cycle, when the data bus voltage decreases, and the next precharge begins.
With reference to FIG. 2B, a write cycle occurs with the inhibiting of the transistors 11 and 12, Precharge PRE being at low logic level. During that interval, write amplifier 10 is enabled by the Enable WMA control signal, which causes full logic level voltage to be applied differentially to the data bus 8. The data bus voltage rises faster than in the earlier case, due to the larger drive capability of the write amplifier as shown by waveform DB/DB*. After a predetermined rise time and time for the voltage on the data bus to become stable, a decoded column address signal Yi is applied to transistors 6, which causes the logic level to be sensed and passed to those charge storage cells that have been addressed via a corresponding wordline.
It has been an objective to raise the speed of operation of DRAMs to accommodate burst rates at least as high as 100 MHz and also to increase the speed of SRAMs. Normal data bus architectures such as the one described above cannot easily operate at 10 ns or less cycles because of the need to charge the capacitance associated with the long data bus conductors, as was seen by the rise times encountered by the signal DB/DB* in FIG. 2A.
In read operations the bitline sense amplifier, which is small, must charge and discharge the appropriate differential data bus lines to develop a large enough differential signal on the opposite end of the memory array that can be detected by the read amplifier. After the data bus is read, its conductors must be precharged in anticipation of the next read cycle.
In write operations, the data bus write amplifier must drive the data bus to full 0 and 1 logic levels to flip the bit line sense amplifier.
For either read or write operations there is not enough time to perform the necessary operations at 100 mHz. For reliability of operation adequate time margin between turning off precharge and turning on Y (column)-access (for example) must be provided.
A synchronous DRAM (SDRAM) has been defined in an effort to provide a structure that can operate at 100 MHz. An SDRAM is in essence a conventional DRAM with a synchronous interface to external circuitry. Synchronous DRAMs employing a clocked rather than a synchronous interface have been defined. SDRAMS are described in the article "Synchronous DRAMs: Designing to the JEDEC standard" in Micron Design Line, volume 2, issue 2, pages 1-5. The standard specifies that multiples of two clocks must occur from one random column-address to the next, which is referred to as the "2N Rule". An SDRAM normally operates in a burst mode, in which data from consecutive column addresses is accessed sequentially. The article states that there are two forms of SDRAM architecture, one referred to as having "prefetch" architecture and the other referred to as having "pipeline" architecture, both producing the same results. The pipeline architecture can issue column-addresses on consecutive clocks, whereas the prefetch architecture is restricted by the 2N rule.
Since the "2N Rule" must be adhered to, the column address can be changed only every second 10 ns clock period. The output data during the clock period following the data from a new address N must be from address N+1. A read cycle is employed which fetches twice as much data from the memory array as is actually required, saving half for output in the following period. In this way the internal data bus cycle rate is halved.
However, this design has a significant impediment since there is no ability to input column address randomly on each clock period.